參數(shù)資料
型號： MPC8343ZQAGDB
廠商： Freescale Semiconductor
文件頁數(shù)： 73/80頁
文件大?。?/td> 0K
描述： IC MPU PWRQUICC II 620-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 620-PBGA（29x29）
包裝： 托盤
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Freescale Semiconductor
75
System Design Information
OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each
other in value. Then, Z0 = (RP + RN) ÷ 2.
Figure 39. Driver Impedance Measurement
Two measurements give the value of this resistance and the strength of the driver current source. First, the
output voltage is measured while driving logic 1 without an external differential termination resistor. The
measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured while driving logic 1
with an external precision differential termination resistor of value Rterm. The measured voltage is
V2 =(1 ÷ (1/R1 +1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1 ÷ V2 –1).
The drive current is then Isource =V1 ÷ Rsource.
Table 61 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal OVDD, 105°C.
21.6
Configuration Pin Multiplexing
The MPC8343EA power-on configuration options can be set through external pull-up or pull-down
resistors of 4.7 k
Ω on certain output pins (see the customer-visible configuration pins). These pins are used
as output only pins in normal operation.
Table 61. Impedance Characteristics
Impedance
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
PCI Signals
(Not Including PCI
Output Clocks)
PCI Output Clocks
(Including
PCI_SYNC_OUT)
DDR DRAM
Symbol
Unit
RN
42 Target
25 Target
42 Target
20 Target
Z0
W
RP
42 Target
25 Target
42 Target
20 Target
Z0
W
Differential
NA
ZDIFF
W
Note: Nominal supply voltages. See Table 1, Tj = 105°C.
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
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