參數(shù)資料
型號(hào)： MPC8343ZQAGDX
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 400 MHz, MICROPROCESSOR, PBGA620
封裝： 29 X 29 MM, 2.46 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-620
文件頁(yè)數(shù)： 6/92頁(yè)
文件大?。?/td> 987K
代理商： MPC8343ZQAGDX
MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 6
14
Freescale Semiconductor
DDR SDRAM
5
DDR SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8343E.
5.1
DDR SDRAM DC Electrical Characteristics
Table 8 provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8343E.
Table 9 provides the DDR capacitance.
Table 8. DDR SDRAM DC Electrical Characteristics
Parameter/Condition
Symbol
Min
Max
Unit
Notes
I/O supply voltage
GVDD
2.375
2.625
V
1
I/O reference voltage
MVREF
0.49
× GV
DD
0.51
× GV
DD
V2
I/O termination voltage
VTT
MVREF – 0.04
MVREF + 0.04
V
3
Input high voltage
VIH
MVREF + 0.18
GVDD + 0.3
V
Input low voltage
VIL
–0.3
MVREF – 0.18
V
Output leakage current
IOZ
–10
10
A4
Output high current (VOUT = 1.95 V)
IOH
–15.2
—
mA
Output low current (VOUT = 0.35 V)
IOL
15.2
—
mA
MVREF input leakage current
IVREF
—5
A
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected
to be equal to MVREF. This rail should track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V
≤ V
OUT ≤ GVDD.
Table 9. DDR SDRAM Capacitance
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS
CIO
68
pF
1
Delta input/output capacitance: DQ, DQS
CDIO
—0.5
pF
1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak to peak) =
0.2 V.
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