
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
84
Freescale Semiconductor
Thermal
Table 66 provides the package thermal characteristics for the 620 29
× 29 mm PBGA of the MPC8347EA.
20.2
Thermal Management Information
For the following sections, PD = (VDD × IDD) + PI/O where PI/O is the power dissipation of the I/O drivers.
See
Table 5 for I/O power dissipation values.
Junction-to-package natural convection on top
ψ
JT
1
°C/W
6
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal, 1 m/s is approximately equal to 200 linear feet per minute (LFM).
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Table 66. Package Thermal Characteristics for PBGA
Parameter
Symbol
Value
Unit
Notes
Junction-to-ambient natural convection on single-layer board (1s)
RθJA
21
°C/W
1, 2
Junction-to-ambient natural convection on four-layer board (2s2p)
RθJMA
15
°C/W
1, 3
Junction-to-ambient (at 200 ft/min) on single-layer board (1s)
RθJMA
17
°C/W
1, 3
Junction-to-ambient (at 200 ft/min) on four-layer board (2s2p)
RθJMA
12
°C/W
1, 3
Junction-to-board thermal
RθJB
6
°C/W
4
Junction-to-case thermal
RθJC
5
°C/W
5
Junction-to-package natural convection on top
ψ
JT
5
°C/W
6
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Table 65. Package Thermal Characteristics for TBGA (continued)
Characteristic
Symbol
Value
Unit
Notes