參數(shù)資料
型號(hào)： MPC8349CZUAGDB
廠商： Freescale Semiconductor
文件頁數(shù)： 78/87頁
文件大小： 0K
描述： IC MPU POWERQUICC II PRO 672TBGA
標(biāo)準(zhǔn)包裝： 24
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 672-LBGA
供應(yīng)商設(shè)備封裝： 672-TBGA（35x35）
包裝： 托盤
配用： MPC8349E-MITX-GP-ND - KIT REFERENCE PLATFORM MPC8349E
MPC8349E-MITXE-ND - BOARD REFERENCE FOR MPC8349
MPC8349EA-MDS-PB-ND - KIT MODULAR DEV SYSTEM MPC8349E
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
8
Freescale Semiconductor
Electrical Characteristics
2.1.2
Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the MPC8349EA. Note that the values in
Table 2 are the recommended and tested operating conditions. Proper device operation outside these
conditions is not guaranteed.
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8349EA.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
Table 2. Recommended Operating Conditions
Parameter
Symbol
Recommended
Value
Unit
Notes
Core supply voltage for 667-MHz core frequency
VDD
1.3 V ± 60 mV
V
1
Core supply voltage
VDD
1.2 V ± 60 mV
V
1
PLL supply voltage for 667-MHz core frequency
AVDD
1.3 V ± 60 mV
V
1
PLL supply voltage
AVDD
1.2 V ± 60 mV
V
1
DDR and DDR2 DRAM I/O voltage
GVDD
2.5 V ± 125 mV
1.8 V ± 90 mV
V—
Three-speed Ethernet I/O supply voltage
LVDD1
3.3 V ± 330 mV
2.5 V ± 125 mV
V—
Three-speed Ethernet I/O supply voltage
LVDD2
3.3 V ± 330 mV
2.5 V ± 125 mV
V—
PCI, local bus, DUART, system control and power
management, I2C, and JTAG I/O voltage
OVDD
3.3 V ± 330 mV
V
—
Note:
1 GV
DD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or
negative direction.
GND
GND – 0.3 V
GND – 0.7 V
Not to Exceed 10%
G/L/OVDD + 20%
G/L/OVDD
G/L/OVDD + 5%
of tinterface
1
1. tinterface refers to the clock period associated with the bus clock interface.
VIH
VIL
Note:
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