參數(shù)資料
型號： MPC8349CZUAGDB
廠商： Freescale Semiconductor
文件頁數(shù)： 81/87頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC II PRO 672TBGA
標準包裝： 24
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1.2V
安裝類型： 表面貼裝
封裝/外殼： 672-LBGA
供應商設備封裝： 672-TBGA（35x35）
包裝： 托盤
配用： MPC8349E-MITX-GP-ND - KIT REFERENCE PLATFORM MPC8349E
MPC8349E-MITXE-ND - BOARD REFERENCE FOR MPC8349
MPC8349EA-MDS-PB-ND - KIT MODULAR DEV SYSTEM MPC8349E
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
82
Freescale Semiconductor
Ordering Information
V2 =(1 ÷ (1/R1 +1/R2)) × Isource. Solving for the output impedance gives Rsource = Rterm × (V1 ÷ V2 –1).
The drive current is then Isource =V1 ÷ Rsource.
Table 65 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD,
nominal OVDD, 105°C.
21.6
Configuration Pin Multiplexing
The MPC8349EA power-on configuration options can be set through external pull-up or pull-down
resistors of 4.7 k
Ω on certain output pins (see the customer-visible configuration pins). These pins are used
as output only pins in normal operation.
However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched
when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal
function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with
the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed
for the output pins.
21.7
Pull-Up Resistor Requirements
The MPC8349EA requires high resistance pull-up resistors (10 k
Ω is recommended) on open-drain pins,
including I2C pins, and IPIC interrupt pins.
For more information on required pull-up resistors and the connections required for the JTAG interface,
refer to application note AN2931, “PowerQUICC Design Checklist.”
22 Ordering Information
This section presents ordering information for the device discussed in this document, and it shows an
example of how the parts are marked.
NOTE
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the MPC8349E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications
(Document Order No. MPC8349EEC).
Table 65. Impedance Characteristics
Impedance
Local Bus, Ethernet,
DUART, Control,
Configuration, Power
Management
PCI Signals
(Not Including PCI
Output Clocks)
PCI Output Clocks
(Including
PCI_SYNC_OUT)
DDR DRAM
Symbol
Unit
RN
42 Target
25 Target
42 Target
20 Target
Z0
W
RP
42 Target
25 Target
42 Target
20 Target
Z0
W
Differential
NA
ZDIFF
W
Note: Nominal supply voltages. See Table 1, Tj = 105°C.
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