參數(shù)資料
型號: MPC8358EVRAGDGA
廠商: Freescale Semiconductor
文件頁數(shù): 14/95頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 668-PBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 668-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 668-PBGA-PGE(29x29)
包裝: 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
21
DDR and DDR2 SDRAM
Figure 5 shows the input timing diagram for the DDR controller.
Figure 5. DDR Input Timing Diagram
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 20 and Table 21 provide the output AC timing specifications and measurement conditions for the
DDR and DDR2 SDRAM interface.
Table 19. DDR and DDR2 SDRAM Input AC Timing Specifications Mode
At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
MDQS—MDQ/MECC input skew per byte
266 MHz
200 MHz
tDISKEW
–1125
–1250
1125
1250
ps
1, 2
Notes:
1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.
2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0
≤ n ≤ 7)
or ECC (MECC[{0...7}] if n = 8).
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications for Source
Synchronous Mode
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.
Parameter8
Symbol1
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
tMCK
610
ns
2
Skew between any MCK to ADDR/CMD
266 MHz
200 MHz
tAOSKEW
–1.1
–1.2
0.3
0.4
ns
3
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
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