
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
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Freescale Semiconductor
JTAG AC Electrical Characteristics
This figure provides the AC test load for TDO and the boundary-scan outputs of the device.
Figure 29. AC Test Load for the JTAG Interface
This figure provides the JTAG clock input timing diagram.
Figure 30. JTAG Clock Input Timing Diagram
This figure provides the TRST timing diagram.
Figure 31. TRST Timing Diagram
This figure provides the boundary-scan timing diagram.
Figure 32. Boundary-Scan Timing Diagram
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
JTAG
tJTKHKL
tJTGR
External Clock
VM
tJTG
tJTGF
VM = Midpoint Voltage (OVDD/2)
TRST
VM = Midpoint Voltage (OVDD/2)
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
VM
tJTDVKH
tJTDXKH
Boundary
Data Outputs
Boundary
Data Outputs
JTAG
External Clock
Boundary
Data Inputs
Output Data Valid
tJTKLDX
tJTKLDZ
tJTKLDV
Input
Data Valid
Output Data Valid