參數(shù)資料
型號: MPC8360ECZUAGDGA
廠商: Freescale Semiconductor
文件頁數(shù): 32/102頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II PRO 740TBGA
標(biāo)準(zhǔn)包裝: 21
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 740-LBGA
供應(yīng)商設(shè)備封裝: 740-TBGA(37.5x37.5)
包裝: 托盤
配用: MPC8360EA-MDS-PB-ND - KIT APPLICATION DEV 8360 SYSTEM
MPC8360E-RDK-ND - BOARD REFERENCE DESIGN FOR MPC
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
Freescale Semiconductor
35
GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications
8.2.5
RGMII and RTBI AC Timing Specifications
This table presents the RGMII and RTBI AC timing specifications.
Table 35. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
Data to clock output skew (at transmitter)
tSKRGTKHDX
tSKRGTKHDV
–0.5
——
0.5
ns
Data to clock input skew (at receiver)
tSKRGDXKH
tSKRGDVKH
1.0
——
2.6
ns
Clock cycle duration
tRGT
7.2
8.0
8.8
ns
Duty cycle for 1000Base-T
tRGTH/tRGT
45
50
55
%
4, 5
Duty cycle for 10BASE-T and 100BASE-TX
tRGTH/tRGT
40
50
60
%
3, 5
Rise time (20–80%)
tRGTR
0.75
ns
Fall time (20–80%)
tRGTF
0.75
ns
GTX_CLK125 reference clock period
tG125
—8.0
ns
GTX_CLK125 reference clock duty cycle
tG125H/tG125
47
53
%
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (Rx) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns can
be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Duty cycle reference is LVDD/2.
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
7. In rev. 2.0 silicon, due to errata, tSKRGTKHDX minimum is –2.3 ns and tSKRGTKHDV maximum is 1 ns for UCC1, 1.2 ns for
UCC2 option 1, and 1.8 ns for UCC2 option 2. In rev. 2.1 silicon, due to errata, tSKRGTKHDX minimum is –0.65 ns for UCC2
option 1 and –0.9 for UCC2 option 2, and tSKRGTKHDV maximum is 0.75 ns for UCC1 and UCC2 option 1 and 0.85 for UCC2
option 2. Refer to Errata QE_ENET10 in Chip Errata for the MPC8360E, Rev. 1. UCC1 does meet tSKRGTKHDX minimum for
rev. 2.1 silicon.
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