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  • 參數(shù)資料
    型號: MPC8360ZUAGDG
    廠商: Freescale Semiconductor
    文件頁數(shù): 10/102頁
    文件大?。?/td> 0K
    描述: IC MPU PWRQUICC II 740-TBGA
    標準包裝: 21
    系列: MPC83xx
    處理器類型: 32-位 MPC83xx PowerQUICC II Pro
    速度: 400MHz
    電壓: 1.2V
    安裝類型: 表面貼裝
    封裝/外殼: 740-LBGA
    供應商設備封裝: 740-TBGA(37.5x37.5)
    包裝: 托盤
    配用: MPC8360EA-MDS-PB-ND - KIT APPLICATION DEV 8360 SYSTEM
    MPC8360E-RDK-ND - BOARD REFERENCE DESIGN FOR MPC
    MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 5
    Freescale Semiconductor
    15
    DC Electrical Characteristics
    4.1
    DC Electrical Characteristics
    This table provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device.
    4.2
    AC Electrical Characteristics
    The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is
    configured in PCI host or PCI agent mode. This table provides the clock input (CLKIN/PCI_CLK) AC timing specifications for
    the device.
    4.3
    Gigabit Reference Clock Input Timing
    This table provides the Gigabit reference clocks (GTX_CLK125) AC timing specifications.
    Table 7. CLKIN DC Electrical Characteristics
    Parameter
    Condition
    Symbol
    Min
    Max
    Unit
    Input high voltage
    VIH
    2.7
    OVDD + 0.3
    V
    Input low voltage
    VIL
    –0.3
    0.4
    V
    CLKIN input current
    0 V
    ≤VIN ≤OVDD
    IIN
    —±10
    μA
    PCI_SYNC_IN input current
    0 V
    ≤VIN ≤0.5V or
    OVDD – 0.5V ≤VIN ≤OVDD
    IIN
    —±10
    μA
    PCI_SYNC_IN input current
    0.5 V
    ≤VIN ≤OVDD – 0.5 V
    IIN
    ±100
    μA
    Table 8. CLKIN AC Timing Specifications
    Parameter/Condition
    Symbol
    Min
    Typical
    Max
    Unit
    Notes
    CLKIN/PCI_CLK frequency
    fCLKIN
    66.67
    MHz
    CLKIN/PCI_CLK cycle time
    tCLKIN
    15
    ns
    CLKIN/PCI_CLK rise and fall time
    tKH, tKL
    0.6
    1.0
    2.3
    ns
    CLKIN/PCI_CLK duty cycle
    tKHK/tCLKIN
    40
    60
    %
    CLKIN/PCI_CLK jitter
    ±150
    ps
    Notes:
    1. Caution: The system, core, USB, security, and 10/100/1000 Ethernet must not exceed their respective maximum or
    minimum operating frequencies.
    2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
    3. Timing is guaranteed by design and characterization.
    4. This represents the total input jitter—short term and long term—and is guaranteed by design.
    5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low
    to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
    Table 9. GTX_CLK125 AC Timing Specifications
    At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV
    Parameter/Condition
    Symbol
    Min
    Typical
    Max
    Unit
    Notes
    GTX_CLK125 frequency
    tG125
    —125
    MHz
    GTX_CLK125 cycle time
    tG125
    —8
    ns
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