參數(shù)資料
型號: MPC8377ECVRAGD
廠商: Freescale Semiconductor
文件頁數(shù): 90/127頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 689-PBGA
標準包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
65
The eye diagram must be valid for any 250 consecutive UIs.
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx
UI.
NOTE
It is recommended that the recovered Tx UI be calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
Figure 42. Minimum Transmitter Timing and Voltage Output Compliance Specifications
15.4.3
Differential Receiver (Rx) Input Specifications
This table defines the specifications for the differential input at all receivers. The parameters are specified
at the component pins.
Table 53. Differential Receiver (Rx) Input Specifications
Parameter
Comments
Symbol
Min
Typical
Max
Units
Note
Unit interval
Each UPERX is 400 ps ± 300
ppm. UPERX does not account
for Spread Spectrum Clock
dictated variations.
UI
399.88
400
400.12
ps
Differential peak-to-peak
output voltage
VPEDPPRX = 2 × |VRX-D+
VRX-D-|
VRX-DIFFp-p
0.175
1.200
V
[De-emphasized Bit]
566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
[Transition Bit]
VTX-DIFFp-p-MIN = 800 mV
0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX)
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
相關(guān)PDF資料
PDF描述
355-020-500-202 CARDEDGE 20POS DL .156 LOPRO BLK
MPC8377CVRANG MPU POWERQUICC II PRO 689-PBGA
HFW22R-1STE1LF CONN FPC/FFC 22POS 1MM R/A SMD
355-020-500-201 CARDEDGE 20POS DL .156 LOPRO BLK
MPC8377CVRAJF MPU POWERQUICC II PRO 689-PBGA
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