參數(shù)資料
型號(hào): MPC8377ECVRAJF
廠商: Freescale Semiconductor
文件頁數(shù): 41/127頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 689-PBGA
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 533MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
20
Freescale Semiconductor
6.2.2
DDR1 and DDR2 SDRAM Output AC Timing Specifications
This table shows the DDR1 and DDR2 SDRAM output AC timing specifications.
Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications
Parameter
Symbol1
Min
Max
Unit
Note
MCK
n cycle time, MCKn/MCKn crossing
tMCK
510
ns
ADDR/CMD output setup with respect to MCK
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHAS
1.95
2.40
3.15
4.20
ns
ADDR/CMD output hold with respect to MCK
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHAX
1.95
2.40
3.15
4.20
ns
MCS
n output setup with respect to MCK
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHCS
1.95
2.40
3.15
4.20
ns
MCS
n output hold with respect to MCK
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHCX
1.95
2.40
3.15
4.20
ns
MCK to MDQS skew
tDDKHMH
–0.6
0.6
ns
MDQ//MDM output setup with respect to MDQS
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHDS,
tDDKLDS
550
800
1100
1200
ps
MDQ//MDM output hold with respect to MDQS
400 MHz data rate
333 MHz data rate
266 MHz data rate
200 MHz data rate
tDDKHDX,
tDDKLDX
700
800
1100
1200
ps
MDQS preamble start
tDDKHMP
–0.5
× tMCK –0.6
–0.5
× tMCK + 0.6
ns
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