參數(shù)資料
型號： MPC8377ECVRAJF
廠商： Freescale Semiconductor
文件頁數(shù)： 91/127頁
文件大小： 0K
描述： MPU POWERQUICC II PRO 689-PBGA
標準包裝： 27
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 533MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 689-BBGA 裸露焊盤
供應商設備封裝： 689-TEPBGA II（31x31）
包裝： 托盤
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
66
Freescale Semiconductor
Minimum receiver eye
width
The maximum interconnect
media and transmitter jitter that
can be tolerated by the receiver
can be derived as
TRX-MAX-JITTER = 1 –
UPEEWRX = 0.6 UI.
TRX-EYE
0.4
——UI
Maximum time between
the jitter median and
maximum deviation from
the median.
Jitter is defined as the
measurement variation of the
crossing points (VPEDPPRX = 0
V) in relation to a recovered Tx
UI. A recovered Tx UI is
calculated over 3500
consecutive unit intervals of
sample data. Jitter is measured
using all edges of the 250
consecutive UI in the center of
the 3500 UI used for calculating
the Tx UI.
TRX-EYE-MEDIAN-to
-MAX-JITTER
—
0.3
UI
AC peak common mode
input voltage
VPEACPCMRX = |VRXD+ –
VRXD-|/2 – VRX-CM-DC
VRX-CM-DC = DC(avg) of |VRX-D+
– VRX-D-|/2
VRX-CM-ACp
—
150
mV
Differential return loss
Measured over 50 MHz to 1.25
GHz with the D+ and D– lines
biased at +300 mV and –300
mV, respectively.
RLRX-DIFF
10
—
dB
Common mode return
loss
Measured over 50 MHz to 1.25
GHz with the D+ and D– lines
biased at 0 V.
RLRX-CM
6—
—
dB
DC differential input
impedance
RX DC differential mode
impedance.
ZRX-DIFF-DC
80
100
120
Ω
DC Input Impedance
Required RX D+ as well as D-
DC impedance (50 ± 20%
tolerance).
ZRX-DC
40
50
60
Ω
Powered down DC input
impedance
Required RX D+ as well as D–
DC impedance when the
receiver terminations do not
have power.
ZRX-HIGH-IMP-DC
200 k
—
Ω
Electrical idle detect
threshold
VPEEIDT = 2 × |VRX-D+ -VRX-D-|
Measured at the package pins
of the receiver
VRX-IDLE-DET-DIFF
p-p
65
—
175
mV
—
Table 53. Differential Receiver (Rx) Input Specifications (continued)
Parameter
Comments
Symbol
Min
Typical
Max
Units
Note
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相關代理商/技術參數(shù)
參數(shù)描述
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