參數(shù)資料
型號(hào): MPC8378EVRAGDA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 79/125頁
文件大?。?/td> 894K
代理商: MPC8378EVRAGDA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
57
11.3.2.2
High-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the SD_CLK and
SD_DAT/CMD signals on the PCB.
0.5
t
SHSCK < tCLK_DELAY + tDATA_DELAY + tOH tSHSIXKH + tINT_CLK_DLY
Eqn. 17
0.5
t
SHSCK tOH + tSHSIXKH tINT_CLK_DLY < tCLK_DELAY + tDATA_DELAY
Eqn. 18
This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle:
10 2.5 + (–1.5) < tCLK_DELAY + tDATA_DELAY
6 < tCLK_DELAY + tDATA_DELAY
11.3.2.3
High-Speed Read Combined Formula
The following equation is the combined formula to calculate the propagation delay range of the SD_CLK and SD_DAT/CMD
signals on the PCB.
0.5
t
SHSCK tOH + tSHSIXKH < tCLK_DELAY + tDATA_DELAY < 1.5tSHSCK tODLY tSHSIVKH
Eqn. 19
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