參數(shù)資料
型號: MPC8378VRANDA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 14/125頁
文件大小: 894K
代理商: MPC8378VRANDA
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
110
22.2
Core PLL Configuration
RCWLR[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock
(core_clk). Table 75 shows the encodings for RCWLR[COREPLL]. COREPLL values that are not listed in Table 75 should be
considered as reserved.
NOTE
Core VCO frequency = core frequency
VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the range of
800–1600 MHz.
Table 74. CSB Frequency Options for Agent Mode
CFG_CLKIN_DIV
at reset1
SPMF
csb_clk :
Input Clock Ratio1
Input Clock Frequency (MHz)2
25
33.33
66.67
csb_clk Frequency (MHz)
Low
0010
2 : 1
133
Low
0011
3 : 1
200
Low
0100
4 : 1
133
267
Low
0101
5 : 1
167
333
Low
0110
6 : 1
150
200
400
Low
0111
7 : 1
175
233
Low
1000
8 : 1
200
267
Low
1001
9 : 1
225
300
Low
1010
10 : 1
250
333
Low
1011
11 : 1
275
367
Low
1100
12 : 1
300
400
Low
1101
13 : 1
325
Low
1110
14 : 1
350
Low
1111
15 : 1
375
Notes:
1. CFG_CLKIN_DIV doubles csb_clk if set high.
2. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
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