參數(shù)資料
型號(hào): MPC8379EVRAGDA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 4/114頁
文件大?。?/td> 1337K
代理商: MPC8379EVRAGDA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
101
Clocking
22.3
Suggested PLL Configurations
Table 76 shows suggested PLL configurations for different input clocks (LBCM = 0).
00
0001
1
1.5:1
2
01
0001
1
1.5:1
4
10
0001
1
1.5:1
8
00
0010
02:1
2
01
0010
02:1
4
10
0010
02:1
8
00
0010
1
2.5:1
2
01
0010
1
2.5:1
4
10
0010
1
2.5:1
8
00
0011
03:1
2
01
0011
03:1
4
10
0011
03:1
8
00
0011
1
3.5:1
2
01
0011
1
3.5:1
4
10
0011
1
3.5:1
8
00
0100
04:1
2
01
0100
04:1
4
10
0100
04:1
8
Note:
1 Core VCO frequency = Core frequency × VCO divider. Note that VCO divider has to be
set properly so that the core VCO frequency is in the range of 800–1600 MHz.
Table 76. Example Clock Frequency Combinations
eLBC 1
e300 Core 1
Ref
1
LBCM DDRCM SVCOD SPMF
Sys
VCO
1,2 CSB
1,3 DDR data
rate
1,4
/2
/4
/8
× 1 × 1.5 × 2 × 2.5 × 3
25.0
0
1
2
5
500
125
250
62.5
31.3
15.6
————
375
25.0
0
1
2
6
600
150
300
75 6
37.5
18.8
375
450
33.3
0
1
2
5
667
167
333
83.3 6
41.6
20.8
333
416
500
33.3
0
1
2
4
533
133
267
66.7
33.3
16.7
333
400
Table 75. e300 Core PLL Configuration (continued)
RCWL[COREPLL]
core_clk : csb_clk Ratio
VCO Divider 1
0–1
2–5
6
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