參數(shù)資料
型號: MPC8379EVRANGA
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689
封裝: 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689
文件頁數(shù): 113/114頁
文件大小: 1337K
代理商: MPC8379EVRANGA
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
98
Freescale Semiconductor
Clocking
As described in Section 22, “Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 73
and Table 74 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.
The RCWL[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 72.
Table 71. System PLL Multiplication Factors
RCWL[SPMF]
System PLL Multiplication Factor
0000
Reserved
0001
Reserved
0010
× 2
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111–1111
× 7 to × 15
Table 72. System PLL VCO Divider
RCWL[SVCOD]
VCO Division Factor
00
4
01
8
10
2
11
1
Table 73. CSB Frequency Options for Host Mode
CFG_CLKIN_DIV
at Reset 1
SPMF
csb_clk :
Input Clock
Ratio 2
Input Clock Frequency (MHz) 2
25
33.33
66.67
csb_clk
Frequency (MHz)
High
0010
2 : 1
133
High
0011
3 : 1
100
High
0100
4 : 1
100
133
High
0101
5 : 1
125
167
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