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| 型號(hào)： | MPC8379EVRANGA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 400 MHz, MICROPROCESSOR, PBGA689 |
| 封裝： | 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-689 |
| 文件頁(yè)數(shù)： | 45/114頁(yè) |
| 文件大?。?/td> | 1337K |
| 代理商： | MPC8379EVRANGA |
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MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
36
Freescale Semiconductor
Local Bus
Table 38 describes the general timing parameters of the local bus interface of the device.
Figure 19 provides the AC test load for the local bus.
Figure 19. Local Bus AC Test Load
Table 39. Local Bus General Timing Parameters—PLL Bypass Mode
Parameter
Symbol1
Min
Max
Unit
Notes
Local bus cycle time
tLBK
15
—
ns
Input setup to local bus clock
tLBIVKH
7.0
—
ns
Input hold from local bus clock
tLBIXKH
1.0
—
ns
LALE output fall to LAD output transition (LATCH
hold time)
tLBOTOT1
1.5
—
ns
LALE output fall to LAD output transition (LATCH
hold time)
tLBOTOT2
3.0
—
ns
LALE output fall to LAD output transition (LATCH
hold time)
tLBOTOT3
2.5
—
ns
Local bus clock to output valid
tLBKHOV
—3.0
ns
Local bus clock to output high impedance for
LAD/LDP
tLBKHOZ
—
4.0
ns
Note:
1 The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case
for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect
to the output (O) going invalid (X) or output hold time.
2 All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3 All signals are measured from LBV
DD/2 of the rising/falling edge of LCLK0 to 0.4 × LBVDD of the signal in question for 3.3-V
signaling levels.
4 Input timings are measured at the pin.
5 t
LBOTOT1 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load on
LAD output pins.
6 t
LBOTOT2 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on LAD
output pins.
7 t
LBOTOT3 should be used when LBCR[AHD] is set and the load on LALE output pin equals to the load on LAD output pins.
8 For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8379EZQAFDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8379EZQAFFA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8379EZQAFGA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8379EZQAGDA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
| MPC8379EZQAGFA | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Processor Hardware Specifications |
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