參數(shù)資料
型號: MPC8379VRANG
廠商: Freescale Semiconductor
文件頁數(shù): 94/117頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 689-PBGA
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 800MHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
78
Freescale Semiconductor
20.3
SerDes Transmitter and Receiver Reference Circuits
This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
Figure 59. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below in
this document based on the application usage:
Note that an external AC coupling capacitor is required for the above three serial transmission protocols
with the capacitor value defined in specification of each protocol section.
21 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions.
21.1
Package Parameters for the MPC8379E TePBGA II
The package parameters are provided in the following list. The package type is 31 mm
× 31 mm,
689 plastic ball grid array (TePBGA II).
Package outline
31 mm
× 31 mm
Interconnects
689
Pitch
1.00 mm
Module height (typical)
2.0 mm to 2.46 mm (maximum)
Solder Balls
3.5% Ag, 96.5% Sn
Ball diameter (typical)
0.60 mm
50
Ω
50
Ω
Receiver
Transmitter
SD1_TX
n or
SD2_TX
n
SD1_TX
n or
SD2_TX
n
SD1_RX
n or
SD2_RX
n
SD1_RX
n or
SD2_RX
n
50
Ω
50
Ω
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