參數資料
型號: MPC852TCZT100A
廠商: Freescale Semiconductor
文件頁數: 12/80頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 100MHZ 256PBGA
標準包裝: 60
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 100MHz
電壓: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應商設備封裝: 256-PBGA(23x23)
包裝: 托盤
MPC852T PowerQUICC Hardware Specifications, Rev. 4
2
Freescale Semiconductor
Overview
1Overview
The MPC852T is a 0.18-micron derivative of the MPC860 PowerQUICC family, and can operate up to
100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a 1.8-V core and a 3.3-V
I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a
versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of
controller applications. It particularly excels in Ethernet control applications, including CPE equipment,
Ethernet routers and hubs, VoIP clients, and WiFi access points.
The MPC852T is a PowerPC architecture-based derivative of the MPC860 Quad Integrated
Communications Controller (PowerQUICC). The CPU on the MPC852T is a MPC8xx core, a 32-bit
microprocessor that implements the PowerPC architecture, incorporating memory management units
(MMUs) and instruction and data caches. The MPC852T is the subset of this family of devices.
2Features
The MPC852T is comprised of three modules that each use a 32-bit internal bus: an MPC8xx core, system
integration unit (SIU), and communication processor module (CPM).
The following list summarizes the key MPC852T features:
Embedded MPC8xx core up to 100 MHz
Maximum frequency operation of the external bus is 66 MHz
— 50/66 MHz core frequencies support both 1:1 and 2:1 modes
— 80/100 MHz core frequencies support 2:1 mode only
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two
32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution.
— 4-Kbyte data cache and 4-Kbyte instruction cache
– 4-Kbyte instruction caches is two-way, set-associative with 128 sets
– 4-Kbyte data cachesis two-way, set-associative with 128 sets
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis
— MMUs with 32-entry TLB, fully associative instruction, and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces, and 16 protection groups
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
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