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| 型號： | MPC852TCZT100A |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 5/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU POWERQUICC 100MHZ 256PBGA |
| 標(biāo)準包裝： | 60 |
| 系列： | MPC8xx |
| 處理器類型： | 32-位 MPC8xx PowerQUICC |
| 速度： | 100MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（23x23） |
| 包裝： | 托盤 |
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MPC852T PowerQUICC Hardware Specifications, Rev. 4
Freescale Semiconductor
13
Layout Practices
The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured
with the mandatory value in Table 6 in the boot code after the reset deasserts.
11 Layout Practices
Each VDD pin on the MPC852T should be provided with a low-impedance path to the board’s supply. Each
GND pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The V
DD power supply should be bypassed to ground using at least four
0.1 F bypass capacitors located as close as possible to the four sides of the package. Each board designed
should be characterized and additional appropriate decoupling capacitors should be used if required. The
capacitor leads and associated printed-circuit traces connecting to chip VDD and GND should be kept to
less than half an inch per capacitor lead. At a minimum, a four-layer board employing two inner layers as
VDD and GND planes should be used.
All output pins on the MPC852T have fast rise and fall times. Printed-circuit (PC) trace interconnection
length should be minimized to minimize undershoot and reflections that these fast output switching times
cause. This recommendation particularly applies to the address and data buses. Maximum PC trace lengths
of six inches are recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances that the PC traces cause. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads, because these loads create higher transient
currents in the VDD and GND circuits. Pull up all unused inputs or signals that are inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins. For more information,
please refer to the MPC866 PowerQUICC Family Reference Manual, Section 14.4.3, “Clock
Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1).”
Table 6. Mandatory Reset Configuration of MPC852T
Register/Configuration
Field
Value
(Binary)
HRCW (Hardware reset configuration word)
HRCW[DBGC]
X1
SIUMCR (SIU module configuration register)
SIUMCR[DBGC]
X1
MBMR (Machine B mode register)
MBMR[GPLB4DIS}
0
PAPAR (Port A pin assignment register)
PAPAR[4–7]
PAPAR[12–15]
0
PADIR (Port A data direction register)
PADIR[4–7]
PADIR[12–15]
1
PBPAR (Port B pin assignment register)
PBPAR[14]
PBPAR[16–23]
PBPAR[26–27]
0
PBDIR (Port B data direction register)
PBDIR[14]
PBDIR[16–23]
PBDIR[26–27]
1
PCPAR (Port C pin assignment register)
PCPAR[8–11]
PCDIR[14]
0
PCDIR (Port C data direction register)
PCDIR[8–11]
PCDIR[14]
1
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