參數(shù)資料
型號: MPC852TVR80
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁數(shù): 13/80頁
文件大?。?/td> 3080K
代理商: MPC852TVR80
MPC852T Hardware Specifications, Rev. 3.1
Freescale Semiconductor
13
Bus Signal Timing
supply pins. For more information, please refer to
MPC866 User’s Manual
, Section 14.4.3, “Clock Synthesizer
Power (V
DDSYN
, V
SSSYN
, V
SSSYN1
).”
12 Bus Signal Timing
The maximum bus speed that the MPC852T supports is 66 MHz.
Table 7
shows the frequency ranges for standard
part frequencies.
Table 9
provides the bus operation timing for the MPC852T at 33, 40, 50 and 66 MHz.
The timing for the MPC852T bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays. CLKOUT assumes a 100-pF load maximum delay
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part
Freq
50MHz
66MHz
Min
Max
Min
Max
Core
Freq
40
50
40
66.67
Bus Freq
40
50
40
66.67
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
Part
Freq
50MHz
66MHz
80MHz
100MHz
Min
Max
Min
Max
Min
Max
Min
Max
Core
Freq
40
50
40
66.67
40
80
40
100
Bus Freq
2:1
20
25
20
33.33
20
40
20
50
Table 9. Bus Operation Timings
Num
Characteristic
33 MHz
40 MHz
50 MHz
66 MHz
Unit
Min
Max
Min
Max
Min
Max
Min
Max
B1
Bus period (CLKOUT) See
Table 7
ns
B1a
EXTCLK to CLKOUT phase skew - If CLKOUT
is an integer multiple of EXTCLK, then the
rising edge of EXTCLK is aligned with the
rising edge of CLKOUT. For a non-integer
multiple of EXTCLK, this synchronization is
lost, and the rising edges of EXTCLK and
CLKOUT have a continuously varying phase
skew.
-2
+2
-2
+2
-2
+2
-2
+2
ns
B1b
CLKOUT frequency jitter peak-to-peak
1
1
1
1
ns
B1c
Frequency jitter on EXTCLK
1
0.50
0.50
0.50
0.50
%
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