參數(shù)資料
型號: MPC8536ECVTAQGA
廠商: Freescale Semiconductor
文件頁數(shù): 9/126頁
文件大?。?/td> 0K
描述: MPU PWRQUICC III 1000MHZ 783PBGA
產(chǎn)品培訓(xùn)模塊: MPC8536E QUICC III Processor
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
其它名稱: MPC8536ECVTAQG
MPC8536ECVTAQG-ND
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Electrical Characteristics
Freescale Semiconductor
106
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges
of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI.
NOTE
The reference impedance for return loss measurements is 50. to ground for both the D+ and
D- line (that is, as measured by a Vector Network Analyzer with 50. probes—see
Figure 71). Note that the series capacitors, CTX, are optional for the return loss
measurement.
Figure 70. Minimum Receiver Eye Timing and Voltage Compliance Specification
2.22.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2 inches of the package
pins, into a test/measurement load shown in the following figure.
NOTE
The allowance of the measurement point to be within 0.2 inches of the package pins is
meant to acknowledge that package/board routing may benefit from D+ and D– not being
exactly matched in length at the package pin boundary.
Figure 71. Compliance Test/Measurement Load
2.23
Clocking
This section describes the PLL configuration of the chip. Note that the platform clock is identical to the core complex bus (CCB)
clock.
VRX-DIFF = 0 mV
(D+, D– Crossing Point
VRX-DIFF = 0 mV
(D+, D– Crossing Point
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
TX
Silicon
+ Package
C = CTX
R = 50
Ω
R = 50
Ω
D+ Package
Pin
D– Package
Pin
D+ Package
Pin
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