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參數(shù)資料
型號： MPC8536ECVTAQGA
廠商： Freescale Semiconductor
文件頁數(shù)： 93/126頁
文件大?。?/td> 0K
描述： MPU PWRQUICC III 1000MHZ 783PBGA
產(chǎn)品培訓(xùn)模塊： MPC8536E QUICC III Processor
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.0GHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
其它名稱： MPC8536ECVTAQG
MPC8536ECVTAQG-ND
Electrical Characteristics
MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
69
This table describes the general timing parameters of the local bus interface at BVDD = 1.8 V DC.
Output hold from local bus clock for LAD/LDP
—
tLBKHOX2
0.8
—
ns
3
Local bus clock to output high Impedance (except LAD/LDP
and LALE)
—tLBKHOZ1
—2.6
ns
5
Local bus clock to output high impedance for LAD/LDP
—
tLBKHOZ2
—2.6
ns
5
Note:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL bypass mode.
3. All signals are measured from BVDD/2 of the rising edge of LSYNC_IN for PLL enabled or internal local bus clock for PLL
bypass mode to 0.4
× BVDD of the signal in question for 2.5-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any change in LAD. tLBOTOT is guaranteed
with LBCR[AHD] = 0.
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
Table 53. Local Bus General Timing Parameters (BVDD = 1.8 V DC)
Parameter
Configuration Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
—
tLBK
7.5
12
ns
2
Local bus duty cycle
—
tLBKH/tLBK
43
57
%
LCLK[n] skew to LCLK[m] or LSYNC_OUT
—tLBKSKEW
150
ps
7
Input setup to local bus clock (except LUPWAIT)
—
tLBIVKH1
2.4
—
ns
3, 4
LUPWAIT input setup to local bus clock
—
tLBIVKH2
1.9
—
ns
3, 4
Input hold from local bus clock (except LUPWAIT)
—
tLBIXKH1
1.1
—
ns
3, 4
LUPWAIT input hold from local bus clock
—
tLBIXKH2
1.1
—
ns
3, 4
LALE output transition to LAD/LDP output transition (LATCH
setup and hold time)
—tLBOTOT
1.2
—
ns
6
Local bus clock to output valid (except LAD/LDP and LALE)
—
tLBKHOV1
—3.2
ns
—
Local bus clock to data valid for LAD/LDP
—
tLBKHOV2
—3.2
ns
3
Local bus clock to address valid for LAD
—
tLBKHOV3
—3.2
ns
3
Local bus clock to LALE assertion
—
tLBKHOV4
—3.2
ns
3
Output hold from local bus clock (except LAD/LDP and LALE)
—
tLBKHOX1
0.9
—
ns
3
Table 52. Local Bus General Timing Parameters (BVDD = 2.5 V DC) (continued)
Parameter
Configuration Symbol 1
Min
Max
Unit
Notes
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MPC8536ECVTATHA 功能描述:微處理器 - MPU 8536 Encrypted RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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