參數(shù)資料
型號(hào): MPC8540CVT667JC
廠商: Freescale Semiconductor
文件頁數(shù): 17/104頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783FCPBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 667MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8540 Integrated Processor Hardware Specifications, Rev. 4.1
2
Freescale Semiconductor
Overview
1 Overview
The following section provides a high-level overview of the MPC8540 features. Figure 1 shows the major
functional units within the MPC8540.
Figure 1. MPC8540 Block Diagram
1.1 Key Features
The following lists an overview of the MPC8540 feature set.
High-performance, 32-bit Book E–enhanced core that implements the Power Architecture
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis. Separate locking for instructions and data
— Memory management unit (MMU) especially designed for embedded applications
— Enhanced hardware and software debug support
— Performance monitor facility (similar to but different from the MPC8540 performance monitor
described in Chapter 18, “Performance Monitor.”
I2C
Local Bus Controller
Programmable
RapidIO Controller
PCI/PCI-X Controller
4ch DMA Controller
DDR SDRAM Controller
256KB
L2-Cache/
SRAM
e500 Core
32 KB L1
I Cache
32 KB L1
D Cache
Core Complex Bus
e500
Coherency
Module
OCeaN
16 Gb/s
RapidIO-8
133 MHz
PCI-X 64b
TSEC
10/100/1G
MII, GMII,TBI,
RTBI, RGMII
MII, GMII,TBI,
RTBI, RGMII
10/100
ENET
MII
DUART
Serial
IRQs
SDRAM
DDR
ROM,
TSEC
10/100/1G
Interrupt Controller
SDRAM,
GPIO
I2C
Controller
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