參數(shù)資料
型號: MPC8544AVTANG
廠商: Freescale Semiconductor
文件頁數(shù): 48/117頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-FCBGA
產(chǎn)品培訓模塊: MPC8544E PowerQUICC™ III
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 800MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應商設備封裝: 783-FCPBGA(29x29)
包裝: 托盤
配用: MPC8544DS-ND - BOARD DEVELOPMENT SYSTEM 8544
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
36
Freescale Semiconductor
Enhanced Three-Speed Ethernet (eTSEC), MII Management
8.7.1
TBI Transmit AC Timing Specifications
Table 34 provides the TBI transmit AC timing specifications.
Figure 19 shows the TBI transmit AC timing diagram.
Figure 19. TBI Transmit AC Timing Diagram
8.7.2
TBI Receive AC Timing Specifications
Table 35 provides the TBI receive AC timing specifications.
Table 34. TBI Transmit AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
GTX_CLK clock period
tGTX
—8.0
ns
GTX_CLK to TCG[9:0] delay time
tTTKHDX
0.2
5.0
ns
2
GTX_CLK rise (20%–80%)
tTTXR
——
1.0
ns
GTX_CLK fall time (80%–20%)
tTTXF
——
1.0
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI
transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid
state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going
high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript
of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. Data valid tTTKHDV to GTX_CLK Min setup time is a function of clock period and max hold time (Min setup = cycle time – Max
delay).
Table 35. TBI Receive AC Timing Specifications
At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.
Parameter/Condition
Symbol1
Min
Typ
Max
Unit
Notes
PMA_RX_CLK[0:1] clock period
tTRX
16.0
ns
PMA_RX_CLK[0:1] skew
tSKTRX
7.5
8.5
ns
GTX_CLK
TCG[9:0]
tTTX
tTTXH
tTTXR
tTTXF
tTTKHDV
tTTKHDX
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