參數(shù)資料
型號： MPC8544AVTANGA
廠商： Freescale Semiconductor
文件頁數(shù)： 36/117頁
文件大?。?/td> 0K
描述： IC MPU POWERQUICC III 783-FCBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 800MHz
電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 6
Freescale Semiconductor
25
Enhanced Three-Speed Ethernet (eTSEC), MII Management
8.3
SGMII Interface Electrical Characteristics
Each SGMII port features a 4-wire AC-coupled serial link from the dedicated SerDes 2 interface of
MPC8544E as shown in Figure 7, where CTX is the external (on board) AC-coupled capacitor. Each output
pin of the SerDes transmitter differential pair features 50-
Ωoutput impedance. Each input of the SerDes
receiver differential pair features 50-
Ωon-die termination to SGND_SRDS2 (xcorevss). The reference
circuit of the SerDes transmitter and receiver is shown in Figure 7.
When an eTSEC port is configured to operate in SGMII mode, the parallel interface’s output signals of this
eTSEC port can be left floating. The input signals should be terminated based on the guidelines described
in Section 21.5, “Connection Recommendations,” as long as such termination does not violate the desired
POR configuration requirement on these pins, if applicable.
When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port.
Instead, SerDes reference clock is required on SD2_REF_CLK and SD2_REF_CLK pins.
8.3.1
AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK
Table 23 lists the SGMII SerDes reference clock AC requirements. Please note that SD2_REF_CLK and
SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock
source.
8.3.2
SGMII Transmitter and Receiver DC Electrical Characteristics
Table 24 and Table 25 describe the SGMII SerDes transmitter and receiver AC-coupled DC electrical
characteristics. Transmitter DC characteristics are measured at the transmitter outputs (SD2_TX[n] and
SD2_TX[n]) as depicted in Figure 8.
Table 23. SD2_REF_CLK and SD2_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Notes
tREF
REFCLK cycle time
—
10 (8)
—
ns
1
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles
——
100
ps
—
tREFPJ
Phase jitter. Deviation in edge location with respect to
mean edge location
–50
—
50
ps
—
Note:
1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR.
Table 24. DC Transmitter Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Supply Voltage
VDD_SRDS2
0.95
1.0
1.05
V
—
Output high voltage
VOH
——
VOS-max + |VOD|–max/2
mV
1
Output low voltage
VOL
VOS-min –|VOD|-max/2
—
mV
Output ringing
VRING
——
10
%
—
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