參數(shù)資料
型號： MPC8547ECPXAUJB
廠商： Freescale Semiconductor
文件頁數(shù)： 13/151頁
文件大?。?/td> 0K
描述： MPU POWERQUICC III 783-PBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.333GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應商設備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
11
Electrical Characteristics
2.1.2
Recommended Operating Conditions
The following table provides the recommended operating conditions for this device. Note that the values
in this table are the recommended and tested operating conditions. Proper device operation outside these
conditions is not guaranteed.
Storage temperature range
TSTG
–55 to 150
C—
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. The –0.3 to 2.75 V range is for DDR and –0.3 to 1.98 V range is for DDR2.
3. The 3.63 V maximum is only supported when the port is configured in GMII, MII, RMII, or TBI modes; otherwise the 2.75 V
the recommended operating conditions per protocol.
4. (M,L,O)VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
Table 2. Recommended Operating Conditions
Characteristic
Symbol
Recommended
Value
Unit
Notes
Core supply voltage
VDD
1.1 V ± 55 mV
V
—
PLL supply voltage
AVDD
1.1 V ± 55 mV
V
Core power supply for SerDes transceivers
SVDD
1.1 V ± 55 mV
V
—
Pad power supply for SerDes transceivers
XVDD
1.1 V ± 55 mV
V
—
DDR and DDR2 DRAM I/O voltage
GVDD
2.5 V ± 125 mV
1.8 V ± 90 mV
V—
Three-speed Ethernet I/O voltage
LVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
V
TVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
—
PCI/PCI-X, DUART, system control and power management, I2C,
Ethernet MII management, and JTAG I/O voltage
OVDD
3.3 V ± 165 mV
V
Local bus I/O voltage
BVDD
3.3 V ± 165 mV
2.5 V ± 125 mV
V—
Input voltage
DDR and DDR2 DRAM signals
MVIN
GND to GVDD
V
DDR and DDR2 DRAM reference
MVREF
GND to GVDD/2
V
Three-speed Ethernet signals
LVIN
TVIN
GND to LVDD
GND to TVDD
V
Local bus signals
BVIN
GND to BVDD
V—
PCI, DUART, SYSCLK, system control and power
management, I2C, Ethernet MII management, and
JTAG signals
OVIN
GND to OVDD
V
Table 1. Absolute Maximum Ratings 1 (continued)
Characteristic
Symbol
Max Value
Unit
Notes
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