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| 型號(hào)： | MPC8547ECPXAUJB |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 43/151頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 783-PBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.333GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 783-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤(pán) |
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
137
System Design Information
the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces
must be kept short, wide and direct.
Figure 60. SerDes PLL Power Supply Filter
Note the following:
AVDD_SRDS must be a filtered version of SVDD.
Signals on the SerDes interface are fed from the XVDD power plane.
22.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the device system, and the device itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and LVDD pin of the
device. These decoupling capacitors must receive their power from separate VDD, TVDD, BVDD, OVDD,
GVDD, LVDD, and GND power planes in the PCB, utilizing short low impedance traces to minimize
inductance. Capacitors must be placed directly under the device using a standard escape pattern as much
as possible. If some caps are to be placed surrounding the part it must be routed with large trace to
minimize the inductance.
These capacitors must have a value of 0.1 F. Only ceramic SMT (surface mount technology) capacitors
must be used to minimize lead inductance, preferably 0402 or 0603 sizes. Besides, it is recommended that
there be several bulk storage capacitors distributed around the PCB, feeding the VDD, TVDD, BVDD,
OVDD, GVDD, and LVDD, planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors must have a low ESR (equivalent series resistance) rating to ensure the quick response time
necessary. They must also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors—100–330 F (AVX TPS tantalum or Sanyo OSCON). However,
customers must work directly with their power regulator vendor for best values, types and quantity of bulk
capacitors.
22.4
SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low
jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is
outlined below.
Only surface mount technology (SMT) capacitors must be used to minimize inductance. Connections from
all capacitors to power and ground must be done with multiple vias to further reduce inductance.
2.2 F 1
0.003 F
1.0
AVDD_SRDS
Note:
1. An 0805 sized capacitor is recommended for system initial bring-up.
SVDD
2.2 F 1
GND
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