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| 型號(hào)： | MPC8548EHXAUJ |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1333 MHz, MICROPROCESSOR, CBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, CERAMIC, BGA-783 |
| 文件頁(yè)數(shù)： | 98/143頁(yè) |
| 文件大?。?/td> | 1460K |
| 代理商： | MPC8548EHXAUJ |
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 8
58
Freescale Semiconductor
PCI/PCI-X
15.2
PCI/PCI-X AC Electrical Specifications
This section describes the general AC timing parameters of the PCI/PCI-X bus. Note that the clock
reference CLK is represented by SYSCLK when the PCI controller is configured for synchronous mode
and by PCIn_CLK when it is configured for asynchronous mode.
Table 52 provides the PCI AC timing specifications at 66 MHz.
Low-level output voltage (OVDD = min, IOL = 2 mA)
VOL
—0.4
V
—
Notes:
1. Ranges listed do not meet the full range of the DC specifications of the
PCI 2.2 Local Bus Specifications.
2. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 52. PCI AC Timing Specifications at 66 MHz
Parameter
Symbol1
Min
Max
Unit
Notes
CLK to output valid
tPCKHOV
—
6.0
ns
2, 3
Output hold from CLK
tPCKHOX
2.0
—
ns
2, 10
CLK to output high impedance
tPCKHOZ
—
14
ns
2, 4, 11
Input setup to CLK
tPCIVKH
3.0
—
ns
2, 5, 10
Input hold from CLK
tPCIXKH
0
—
ns
2, 5, 10
REQ64 to HRESET 9 setup time
tPCRVRH
10
× tSYS
—
clocks
6, 7, 11
HRESET to REQ64 hold time
tPCRHRX
050
ns
7, 11
HRESET high to first FRAME assertion
tPCRHFV
10
—
clocks
8, 11
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI/PCI-X
timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, tSYS, reference
(K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI/PCI-X timing (PC) with respect to the time hard
reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the
PCI 2.2 Local Bus Specifications.
3. All PCI signals are measured from OVDD/2 of the rising edge of SYSCLK or PCI_CLKn to 0.4 × OVDD of the signal in question
for 3.3-V PCI signaling levels.
4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
5. Input timings are measured at the pin.
6. The timing parameter tSYS indicates the minimum and maximum CLK cycle times for the various specified frequencies. The
system clock period must be kept within the minimum and maximum defined ranges. For values see Section 20, “Clocking.”
7. The setup and hold time is with respect to the rising edge of HRESET.
8. The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local Bus
Specifications.
9. The reset assertion timing requirement for HRESET is 100
μs.
10.Guaranteed by characterization.
11.Guaranteed by design.
Table 51. PCI/PCI-X DC Electrical Characteristics1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8548EHXAVH | 制造商:Freescale Semiconductor 功能描述:MPU RISC 32BIT CMOS 1.5GHZ 1.8V/2.5V/3.3V - Bulk |
| MPC8548EHXAVK | 制造商:Freescale Semiconductor 功能描述:PQ38 8548E - Bulk |
| MPC8548EPXANJB | 制造商:Freescale Semiconductor 功能描述:PQ38 8548 - Bulk |
| MPC8548EPXAQGA | 制造商:Freescale Semiconductor 功能描述:MPC85XX RISC 32-BIT CMOS 1GHZ 1.8V/2.5V/3.3V 783-PIN BGA TRA - Bulk |
| MPC8548EPXAQGB | 功能描述:微處理器 - MPU FG PQ38 8548 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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