參數(shù)資料
型號(hào): MPC8548EHXAUJ
廠商: Freescale Semiconductor
文件頁數(shù): 36/151頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC III 783-FCCBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
130
Freescale Semiconductor
Clocking
20 Clocking
This section describes the PLL configuration of the device. Note that the platform clock is identical to the
core complex bus (CCB) clock.
20.1
Clock Ranges
Table 75 through Table 77 provide the clocking specifications for the processor cores and Table 78,
through Table 80 provide the clocking specifications for the memory bus.
Table 75. Processor Core Clocking Specifications (MPC8548E and MPC8547E)
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1000 MHz
1200 MHz
1333 MHz
Min
Max
Min
Max
Min
Max
e500 core processor frequency
800
1000
800
1200
800
1333
MHz
1, 2
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
Table 76. Processor Core Clocking Specifications (MPC8545E)
Characteristic
Maximum Processor Core Frequency
Unit
Notes
800 MHz
1000 MHz
1200 MHz
Min
Max
Min
Max
Min
Max
e500 core processor frequency
800
1000
800
1200
MHz
1, 2
Notes:
1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
2.)The minimum e500 core frequency is based on the minimum platform frequency of 333 MHz.
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