參數(shù)資料
型號： MPC8548EHXAUJ
廠商： Freescale Semiconductor
文件頁數(shù)： 89/151頁
文件大?。?/td> 0K
描述： IC MPU PWRQUICC III 783-FCCBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.333GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
42
Freescale Semiconductor
Ethernet Management Interface Electrical Characteristics
Figure 21 shows the MII management AC timing diagram.
Figure 21. MII Management Interface Timing Diagram
MDC fall time
tMDHF
—10
ns
4
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (fCCB). The actual
ECn_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
device’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform Frequency
(CCB)
(2 × Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if
MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, fMDC = 533) (2 × 4 × 8) = 533) 64 =
8.3 MHz. That is, for a system running at a particular platform frequency (fCCB), the ECn_MDC output clock frequency can be
programmed between maximum fMDC = fCCB 64 and minimum fMDC = fCCB 448. See 14.5.3.6.6, “MII Management
Configuration Register (MIIMCFG),” in the MPC8548E PowerQUICC III Integrated Processor Family Reference Manual for
more detail.
3.The maximum ECn_MDC output clock frequency is defined based on the maximum platform frequency for device (533 MHz)
divided by 64, while the minimum ECn_MDC output clock frequency is defined based on the minimum platform frequency for
device (333 MHz) divided by 448, following the formula described in Note 2 above.
4. Guaranteed by design.
5. tCCB is the platform (CCB) clock period.
Table 37. MII Management AC Timing Specifications (continued)
At recommended operating conditions with OVDD is 3.3 V ± 5%.
Parameter
Symbol1
Min
Typ
Max
Unit
Notes
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
(Input)
(Output)
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MPC8548EHXAVH 制造商:Freescale Semiconductor 功能描述:MPU RISC 32BIT CMOS 1.5GHZ 1.8V/2.5V/3.3V - Bulk
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