參數(shù)資料
型號: MPC8548EVTATGB
廠商: Freescale Semiconductor
文件頁數(shù): 123/151頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783-PBGA
產(chǎn)品培訓模塊: MPC8548 PowerQUICC III Processors
標準包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.2GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應商設備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
73
PCI Express
17 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8548E.
17.1
DC Requirements for PCI Express SD_REF_CLK and
SD_REF_CLK
17.2
AC Requirements for PCI Express SerDes Clocks
Table 55 lists the AC requirements for the PCI Express SerDes clocks.
17.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
17.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer see PCI Express Base
Specification. Rev. 1.0a.
17.4.1
Differential Transmitter (TX) Output
Table 56 defines the specifications for the differential output at all transmitters (TXs). The parameters are
specified at the component pins.
Table 55. SD_REF_CLK and SD_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typ
Max
Unit
Notes
tREF
REFCLK cycle time
10
ns
1
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles.
100
ps
tREFPJ
Phase jitter. Deviation in edge location with respect to mean edge
location.
–50
50
ps
Note:
1. Typical based on PCI Express Specification 2.0.
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