參數(shù)資料
型號: MPC8555PXAPF
廠商: Freescale Semiconductor
文件頁數(shù): 77/88頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC III 783-FCPBGA
標(biāo)準(zhǔn)包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 833MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
配用: CWH-PPC-8540N-VE-ND - KIT EVAL SYSTEM MPC8540
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
79
System Design Information
Figure 50 shows the PLL power supply filter circuit.
Figure 50. PLL Power Supply Filter Circuit
17.3
Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8555E can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8555E system, and the
MPC8555E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that
the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins
of the MPC8555E. These decoupling capacitors should receive their power from separate VDD, OVDD,
GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance.
Capacitors may be placed directly under the device using a standard escape pattern. Others may surround
the part.
These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 F (AVX TPS tantalum or Sanyo
OSCON).
17.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of
the MPC8555E.
17.5
Output Buffer DC Impedance
The MPC8555E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I2C).
To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
or GND. Then, the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 51). The
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
VDD
AVDD (or L2AVDD)
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
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MPC8555VTAQF 功能描述:IC MPU POWERQUICC III 783-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC85xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點(diǎn):- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA(29x29) 包裝:托盤