參數(shù)資料
型號(hào)： MPC755CVT400LE
廠商： Freescale Semiconductor
文件頁數(shù)： 1/56頁
文件大小： 0K
描述： MCU HIP4DP 400MHZ 360-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC7xx
處理器類型： 32-位 MPC7xx PowerPC
速度： 400MHz
電壓： 2V
安裝類型： 表面貼裝
封裝/外殼： 360-BBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 360-FCCBGA（25x25）
包裝： 托盤
Freescale Semiconductor, Inc., 2006. All rights reserved.
Freescale Semiconductor
Technical Data
This document is primarily concerned with the MPC755;
however, unless otherwise noted, all information here also
applies to the MPC745. The MPC755 and MPC745 are
reduced instruction set computing (RISC) microprocessors
that implement the PowerPC instruction set architecture.
This document describes pertinent physical characteristics of
the MPC755. For information on specific MPC755 part
numbers covered by this or other specifications, see
characteristics of the processor, refer to the MPC750 RISC
Microprocessor Family User’s Manual.
To locate any published errata or updates for this document,
refer to the website listed on the back cover of this document.
1
Overview
The MPC755 is targeted for low-cost, low-power systems
and supports the following power management
features—doze, nap, sleep, and dynamic power
management. The MPC755 consists of a processor core and
an internal L2 tag combined with a dedicated L2 cache
interface and a 60x bus. The MPC745 is identical to the
MPC755 except it does not support the L2 cache interface.
Figure 1 shows a block diagram of the MPC755.
Document Number: MPC755EC
Rev. 8, 02/2006
Contents
MPC755
RISC Microprocessor
Hardware Specifications
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