參數(shù)資料
型號： MPC8560CPX833LC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 883 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù)： 39/108頁
文件大?。?/td> 1238K
代理商： MPC8560CPX833LC
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
36
Freescale Semiconductor
Local Bus
Table 32 describes the general timing parameters of the local bus interface of the MPC8560 with the DLL
bypassed.
Local bus clock to output high impedance
for LAD/LDP
TSEC2_TXD[6:5] = 00
tLBKHOZ2
—
2.5
ns
7, 9
TSEC2_TXD[6:5] = 11
(default)
3.8
Notes:
1.The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local
bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this
case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with
respect to the output (O) going invalid (X) or output hold time.
2.All timings are in reference to LSYNC_IN for DLL enabled mode.
3.Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OVDD/2.
4.All signals are measured from OVDD/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OVDD of the signal in question
for 3.3-V signaling levels.
5.Input timings are measured at the pin.
6.The value of tLBOTOT is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5].
7.
For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
8.Guaranteed by characterization.
9.Guaranteed by design.
Table 32. Local Bus General Timing Parameters—DLL Bypassed
Parameter
POR Configuration
Symbol 1
Min
Max
Unit
Notes
Local bus cycle time
—
tLBK
6.0
—
ns
2
Internal launch/capture clock to LCLK delay
—
tLBKHKT
2.3
3.9
ns
8
LCLK[n] skew to LCLK[m] or LSYNC_OUT
—
tLBKSKEW
—
150
ps
3, 9
Input setup to local bus clock (except
LUPWAIT)
—tLBIVKH1
5.7
—
ns
4, 5
LUPWAIT input setup to local bus clock
—
tLBIVKH2
5.6
—
ns
4, 5
Input hold from local bus clock (except
LUPWAIT)
—tLBIXKH1
-1.8
—
ns
4, 5
LUPWAIT input hold from local bus clock
—
tLBIXKH2
-1.3
—
ns
4, 5
LALE output transition to LAD/LDP output
transition (LATCH hold time)
—tLBOTOT
1.5
—
ns
6
Local bus clock to output valid (except
LAD/LDP and LALE)
TSEC2_TXD[6:5] = 00
tLBKLOV1
—-0.3
ns
4
TSEC2_TXD[6:5] = 11
(default)
1.2
Table 31. Local Bus General Timing Parameters—DLL Enabled (continued)
Parameter
POR Configuration
Symbol 1
Min
Max
Unit
Notes
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