參數(shù)資料
型號(hào)： MPC8560PXAPFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁(yè)數(shù)： 75/108頁(yè)
文件大?。?/td> 2170K
代理商： MPC8560PXAPFB
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
69
RapidIO
The compliance of receiver input signals RD[0:15] and RFRAME with their minimum data valid window (DV)
specification shall be determined by generating an eye pattern for each of the data signals and comparing the eye
pattern of each data signal with the RapidIO receive mask shown in Figure 46. The value of X2 used to construct
the mask shall be (1 – DVmin)/2. The ±100 mV minimum data valid and ±600 mV maximum input voltage values
are from the DC specification. A signal is compliant with the data valid window specification if and only if the
receive mask can be positioned on the signal’s eye pattern such that the eye pattern falls entirely within the unshaded
portion of the mask.
Figure 46. RapidIO Receive Mask
The eye pattern for a data signal is generated by making a large number of recordings of the signal and then
overlaying the recordings. The number of recordings used to generate the eye shall be large enough that further
increasing the number of recordings used does not cause the resulting eye pattern to change from one that complies
with the RapidIO receive mask to one that does not. Each data signal in the interface shall be carrying random or
pseudo-random data when the recordings are made. If pseudo-random data is used, the length of the pseudo-random
sequence (repeat length) shall be long enough that increasing the length of the sequence does not cause the resulting
Table 52. RapidIO Receiver AC Timing Specifications—1 Gbps Data Rate
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Duty cycle of the clock input
DC
47
53
%
1, 5
Data valid
DV
425
—
ps
2
Allowable static skew between any two data
inputs within a 8-/9-bit group
tDPAIR
—
300
ps
3
Allowable static skew of data inputs to associated
clock
tSKEW,PAIR
–200
200
ps
4
Notes:
1.Measured at VID = 0 V.
2.Measured using the RapidIO receive mask shown in Figure 46.
3.See Figure 49.
5.Guaranteed by design.
X2
600
0
100
–100
–600
1–X2
DV
V
ID
(m
V)
Time (UI)
01
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MPC8560VT667LC 功能描述:微處理器 - MPU PQ 3 8560-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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