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    參數(shù)資料
    型號: MPC8560VT833FB
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 883 MHz, RISC PROCESSOR, PBGA783
    封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
    文件頁數(shù): 76/108頁
    文件大?。?/td> 1379K
    代理商: MPC8560VT833FB
    MPC8560 Integrated Processor Hardware Specifications, Rev. 4
    Freescale Semiconductor
    7
    Overview
    — MII management interface for control and status
    — Programmable CRC generation and checking
    — Ability to force allocation of header information and buffer descriptors into L2 cache.
    OCeaN switch fabric
    — Four-port crossbar packet switch
    — Reorders packets from a source based on priorities
    — Reorders packets to bypass blocked packets
    — Implements starvation avoidance algorithms
    — Supports packets with payloads of up to 256 bytes
    Integrated DMA controller
    — Four-channel controller
    — All channels accessible by both the local and remote masters
    — Extended DMA functions (advanced chaining and striding capability)
    — Support for scatter and gather transfers
    — Misaligned transfer capability
    — Interrupt on completed segment, link, list, and error
    — Supports transfers to or from any local memory or I/O port
    — Selectable hardware-enforced coherency (snoop/no-snoop)
    — Ability to start and flow control each DMA channel from external 3-pin interface
    — Ability to launch DMA from single write transaction
    PCI/PCI-X controller
    — PCI 2.2 and PCI-X 1.0 compatible
    — 64- or 32-bit PCI port supports at 16 to 66 MHz
    — 64-bit PCI-X support up to 133 MHz
    — Host and agent mode support
    — 64-bit dual address cycle (DAC) support
    — PCI-X supports multiple split transactions
    — Supports PCI-to-memory and memory-to-PCI streaming
    — Memory prefetching of PCI read accesses
    — Supports posting of processor-to-PCI and PCI-to-memory writes
    — PCI 3.3-V compatible
    — Selectable hardware-enforced coherency
    Power management
    — Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O
    — Supports power saving modes: doze, nap, and sleep
    — Employs dynamic power management, which automatically minimizes power consumption of
    blocks when they are idle.
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