參數(shù)資料
型號: MPC8568VTAUJJ
廠商: Freescale Semiconductor
文件頁數(shù): 131/139頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023-PBGA
標(biāo)準包裝: 24
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
91
SPI
18 SPI
This section describes the DC and AC electrical specifications for the SPI of the MPC8568E.
18.1
SPI DC Electrical Characteristics
Table 69 provides the DC electrical characteristics for the MPC8568E SPI.
18.2
SPI AC Timing Specifications
Table 70 and provide the SPI input and output AC timing specifications.
Figure 57 provides the AC test load for the SPI.
Figure 57. SPI AC Test Load
Table 69. SPI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –6.0 mA
2.4
V
Output low voltage
VOL
IOL = 6.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Input high voltage
VIH
—2.0
OVDD+0.3
V
Input low voltage
VIL
—-0.3
0.8
V
Input current
IIN
0 V
≤ VIN ≤ OVDD
± 10
μA
Table 70. SPI AC Timing Specifications 1
Characteristic
Symbol 2
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
tNIKHOV
06
ns
SPI outputs—Slave mode (external clock) delay
tNEKHOV
28
ns
SPI inputs—Master mode (internal clock) input setup time
tNIIVKH
4—
ns
SPI inputs—Master mode (internal clock) input hold time
tNIIXKH
0—
ns
SPI inputs—Slave mode (external clock) input setup time
tNEIVKH
4—
ns
SPI inputs—Slave mode (external clock) input hold time
tNEIXKH
2—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from
the high state (H) until outputs (O) are valid (V).
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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