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| 型號： | MPC8569EVTAUNLB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, PLASTIC, BGA-783 |
| 文件頁數(shù)： | 118/126頁 |
| 文件大小： | 2847K |
| 代理商： | MPC8569EVTAUNLB |
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Serial RapidIO (SRIO)
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
91
2.11.3
DC Requirements for Serial RapidIO
This section explains the DC requirements for the Serial RapidIO interface.
2.11.3.1
DC Requirements for Serial RapidIO SD_REF_CLK and SD_REF_CLK
The characteristics and DC requirements of the separate SerDes reference clocks of the SRIO interface are described in
2.11.3.2
DC Serial RapidIO Timing Transmitter Specifications
The LP-serial transmitter electrical and timing specifications are given in the following sections.
The differential return loss, S11, of the transmitter in each case are better than the following:
–10 dB for (Baud Frequency)
÷ 10 < Freq(f) < 625 MHz
–10 dB + 10log(f
÷ 625 MHz) dB for 625 MHz ≤Freq(f) ≤Baud Frequency
The reference impedance for the differential return loss measurements is 100-
Ωresistive. Differential return loss includes
contributions from on-chip circuitry, chip packaging, and any off-chip components related to the driver. The output impedance
requirement applies to all valid output levels.
It is recommended that the 20%–80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have
a minimum value 60 ps.
It is recommended that the timing skew at the output of an LP-serial transmitter between the two signals that comprise a
differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB, and 15 ps at 3.125 GB.
The following table defines the serial RapidIO transmitter DC specifications.
2.11.3.3
DC Serial RapidIO Receiver Specifications
The LP-serial receiver electrical and timing specifications are given in the following sections.
Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode return loss better than
6 dB from 100 MHz to (0.8)
× (baud frequency). This includes contributions from on-chip circuitry, the chip package, and any
off-chip components related to the receiver. AC coupling components are included in this requirement. The reference impedance
for return loss measurements is 100-
Ωresistive for differential return loss and 25-Ω resistive for common mode.
Table 52. SRIO Transmitter DC Timing Specifications—1.25, 2.5, and 3.125 GBauds
At recommended operating conditions with XVDD = 1.0 V ± 3%. and 1.1 V ± 3%
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Output voltage
VO
–0.40
—
2.30
V
1
Long-run differential output voltage
VDIFFPP
800
—
1600
mV p-p
—
Short-run differential output voltage
VDIFFPP
500
—
1000
mV p-p
—
Note:
1. Voltage relative to COMMON of either signal comprising a differential pair.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MPC8569VTAQLJB | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 8569 ST 1067/667/533 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MPC8569VTAUNLB | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 8569 ST 1333/667/533 r2.1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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