參數(shù)資料
型號: MPC8572CVTAVNE
廠商: Freescale Semiconductor
文件頁數(shù): 39/138頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.5GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
133
System Design Information
SD2_TX[3:0]
SD2_TX[3:0]
Reserved pins: AF26, AF27
The following pins must be connected to XGND_SRDS2:
SD2_RX[3:0]
SD2_RX[3:0]
SD2_REF_CLK
SD2_REF_CLK
The POR configuration pin cfg_srds_sgmii_en on UART_RTS[1] can be used to power down SerDes 2
block for power saving. Note that both SVDD_SRDS2 and XVDD_SRDS2 must remain powered.
21.10.4 SerDes 2 Interface (SGMII) Partly Unused
If only part of the high speed SerDes 2 interface (SGMII) pins are used, the remaining high-speed serial
I/O pins should be terminated as described in this section.
The following pins must be left unconnected (float):
SD2_TX[3:0]
SD2_TX[3:0]
Reserved pins: AF26, AF27
The following pins must be connected to XGND_SRDS2:
SD2_RX[3:0]
SD2_RX[3:0]
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