參數(shù)資料
型號: MPC8572ECVTARLB
廠商: Freescale Semiconductor
文件頁數(shù): 64/138頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.067GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
31
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
Figure 7 and Figure 8 show the FIFO timing diagrams.
Figure 7. FIFO Transmit AC Timing Diagram
Rise time TX_CLK (20%–80%)
tFITR
0.75
ns
Fall time TX_CLK (80%–20%)
tFITF
0.75
ns
FIFO data TXD[7:0], TX_ER, TX_EN setup time to GTX_CLK
tFITDV
2.0
——ns
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold time
tFITDX
0.5
3.0
ns
Notes:
1. The minimum cycle period (or maximum frequency) of the TX_CLK is dependent on the maximum platform frequency of the
speed bins the part belongs to as well as the FIFO mode under operation. Refer to Section 4.5, “Platform to eTSEC FIFO
Restrictions,” for more detailed description.
Table 26. FIFO Mode Receive AC Timing Specification
At recommended operating conditions with LVDD/TVDD of 2.5V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
RX_CLK clock period1
tFIR
5.3
8.0
100
ns
RX_CLK duty cycle
tFIRH/tFIR
45
50
55
%
RX_CLK peak-to-peak jitter
tFIRJ
250
ps
Rise time RX_CLK (20%–80%)
tFIRR
0.75
ns
Fall time RX_CLK (80%–20%)
tFIRF
0.75
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
tFIRDV
1.5
——ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
tFIRDX
0.5
——ns
1. The minimum cycle period (or maximum frequency) of the RX_CLK is dependent on the maximum platform frequency of the
speed bins the part belongs to as well as the FIFO mode under operation. Refer to Section 4.5, “Platform to eTSEC FIFO
Restrictions,” for more detailed description.
Table 25. FIFO Mode Transmit AC Timing Specification (continued)
At recommended operating conditions with LVDD/TVDD of 2.5V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
tFIT
tFITH
tFITF
tFITDX
TXD[7:0]
TX_EN
GTX_CLK
TX_ER
tFITDV
tFITR
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