參數(shù)資料
型號： MPC8572VTARLE
廠商： Freescale Semiconductor
文件頁數(shù)： 63/138頁
文件大小： 0K
描述： MPU POWERQUICC III 1023FCPBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.067GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應商設備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
30
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
8.2
FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing
Specifications
The AC timing specifications for FIFO, GMII, MII, TBI, RGMII, RMII and RTBI are presented in this
section.
8.2.1
FIFO AC Specifications
The basis for the AC specifications for the eTSEC’s FIFO modes is the double data rate RGMII and RTBI
specifications, because they have similar performance and are described in a source-synchronous fashion
like FIFO modes. However, the FIFO interface provides deliberate skew between the transmitted data and
source clock in GMII fashion.
When the eTSEC is configured for FIFO modes, all clocks are supplied from external sources to the
relevant eTSEC interface. That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK,
while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back on
the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is intended
that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a source-
synchronous timing reference. Typically, the clock edge that launched the data can be used, because the
clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is a
relationship between the maximum FIFO speed and the platform (CCB) frequency. For more information
Table 25 and Table 26 summarize the FIFO AC specifications.
Input high current
(VIN = LVDD, VIN = TVDD)
IIH
—10
μA
Input low current
(VIN = GND)
IIL
–15
—
μA
Note:
1 LV
DD supports eTSECs 1 and 2.
2 TV
DD supports eTSECs 3 and 4 or FEC.
3 Note that the symbol V
IN, in this case, represents the LVIN and TVIN symbols referenced in Table 1.
Table 25. FIFO Mode Transmit AC Timing Specification
At recommended operating conditions with LVDD/TVDD of 2.5V ± 5%
Parameter/Condition
Symbol
Min
Typ
Max
Unit
TX_CLK, GTX_CLK clock period1
tFIT
5.3
8.0
100
ns
TX_CLK, GTX_CLK duty cycle
tFITH/tFIT
45
50
55
%
TX_CLK, GTX_CLK peak-to-peak jitter
tFITJ
——
250
ps
Table 24. MII, GMII, RMII, RGMII, TBI, RTBI, and FIFO DC Electrical Characteristics (continued)
Parameters
Symbol
Min
Max
Unit
Notes
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