參數(shù)資料
型號(hào): MPC8572VTARLE
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 87/138頁(yè)
文件大小: 0K
描述: MPU POWERQUICC III 1023FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.067GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
52
Freescale Semiconductor
Ethernet Management Interface Electrical Characteristics
Figure 28 shows the MII management AC timing diagram.
Figure 28. MII Management Interface Timing Diagram
ECn_MDIO to ECn_MDC hold time
tMDDXKH
0—
ns
ECn_MDC rise time
tMDCR
10
ns
4
ECn_MDC fall time
tMDHF
10
ns
4
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the eTSEC system clock speed, which is half of the Platform Frequency (fCCB). The actual
ECn_MDC output clock frequency for a specific eTSEC port can be programmed by configuring the MgmtClk bit field of
MPC8572E’s MIIMCFG register, based on the platform (CCB) clock running for the device. The formula is: Platform
Frequency (CCB)/(2*Frequency Divider determined by MIICFG[MgmtClk] encoding selection). For example, if
MIICFG[MgmtClk] = 000 and the platform (CCB) is currently running at 533 MHz, fMDC = 533/(2*4*8) = 533/64 = 8.3 MHz.
That is, for a system running at a particular platform frequency (fCCB), the ECn_MDC output clock frequency can be
programmed between maximum fMDC = fCCB/64 and minimum fMDC = fCCB/448. Refer to MPC8572E reference manual’s
MIIMCFG register section for more detail.
3. The maximum ECn_MDC output clock frequency is defined based on the maximum platform frequency for MPC8572E
(600 MHz) divided by 64, while the minimum ECn_MDC output clock frequency is defined based on the minimum platform
frequency for MPC8572E (400 MHz) divided by 448, following the formula described in Note 2 above. The typical
ECn_MDC output clock frequency of 2.5 MHz is shown for reference purpose per IEEE 802.3 specification.
4. Guaranteed by design.
5. tplb_clk is the platform (CCB) clock.
Table 45. MII Management AC Timing Specifications (continued)
At recommended operating conditions with LVDD/TVDD of 3.3 V ± 5% or 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Notes
ECn_MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
ECn_MDIO
(Input)
(Output)
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