參數(shù)資料
型號(hào): MPC8572VTAVNB
廠商: Freescale Semiconductor
文件頁數(shù): 132/138頁
文件大小: 0K
描述: MPU POWERQUICC III 1023-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.5GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
93
Serial RapidIO
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the
transmitter shall fall entirely within the unshaded portion of the transmitter output compliance mask shown
in Figure 58 with the parameters specified in Figure 71 when measured at the output pins of the device and
the device is driving a 100
Ω +/–5% differential resistive load. The output eye pattern of an LP-Serial
transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol interference) need
only comply with the Transmitter Output Compliance Mask when pre-emphasis is disabled or minimized.
Table 69. Long Run Transmitter AC Timing Specifications—2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
VO
–0.40
2.30
Volts
Voltage relative to COMMON of
either signal comprising a
differential pair
Differential Output Voltage
VDIFFPP
800
1600
mV p-p
Deterministic Jitter
JD
0.17
UI p-p
Total Jitter
JT
0.35
UI p-p
Multiple output skew
SMO
1000
ps
Skew at the transmitter output
between lanes of a multilane
link
Unit Interval
UI
400
ps
+/- 100 ppm
Table 70. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
VO
–0.40
2.30
Volts
Voltage relative to COMMON of
either signal comprising a
differential pair
Differential Output Voltage
VDIFFPP
800
1600
mV p-p
Deterministic Jitter
JD
0.17
UI p-p
Total Jitter
JT
0.35
UI p-p
Multiple output skew
SMO
1000
ps
Skew at the transmitter output
between lanes of a multilane
link
Unit Interval
UI
320
ps
+/- 100 ppm
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