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參數(shù)資料
| 型號(hào)： | MPC859P |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerQUICC⑩ Family Technical Summary |
| 中文描述： | ⑩家庭技術(shù)的PowerQUICC綜述 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 287K |
| 代理商： | MPC859P |
2
MPC859P/859T/859DSL PowerQUICC Family Technical Summary
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Features
1.1
Features
The following list summarizes the key MPC859P/859T/859DSL Family features:
Embedded MPC8xx core up to 133 MHz
Maximum frequency operation of the external bus is 66 MHz
— The 133MHz/100MHz core frequencies support 2:1 mode only
— The 50MHz/66MHz core frequencies support both 1:1 and 2:1 modes
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with 32, 32-bit
general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1).
– 16-Kbyte instruction cache (MPC859P) is four-way, set-associative with 256 sets;4-Kbyte
instruction cache (MPC859T and MPC859DSL) is two-way, set-associative with 128 sets.
– 8-Kbyte data cache (MPC859P) is two-way, set-associative with 256 sets; 4-Kbyte data
cache (MPC859T and MPC859DSL) is two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks.
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups
The MPC859P/859T/859DSL Family provides enhanced ATM functionality as found on the
MPC866. The MPC859P/859T/859DSL adds major new features available in “enhanced SAR”
(ESAR) mode, including the following:
— Improved operation, administration and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
— Port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
— Optional statistical cell counters per PHY
Table 1. MPC859T Family
Part
Cache
Ethernet
SCC
ATM Support
Instruction
Cache
Data Cache
10Base
T
10/100
MPC859P
16 Kbyte
8 Kbyte
1
1
1
Serial ATM and UTOPIA
Interface
MPC859T
4 Kbyte
4 Kbyte
1
1
1
Serial ATM and UTOPIA
Interface
MPC859DSL
4 Kbyte
4 Kbyte
1
1
1
Serial ATM and UTOPIA
Interface
F
Freescale Semiconductor, Inc.
n
.
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| MPC859PCZP100A | 功能描述:微處理器 - MPU POWER QUICC I HIP6W RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC859PVR100A | 功能描述:微處理器 - MPU PQ I HIP6W NO-PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC859PVR133A | 功能描述:微處理器 - MPU PQ I HIP6W NO-PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC859PZP100A | 功能描述:微處理器 - MPU POWER QUICC I HIP6W RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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