參數(shù)資料
型號: MPC859PZP133
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Hardware Specifications
中文描述: 硬件規(guī)格
文件頁數(shù): 15/92頁
文件大小: 1274K
代理商: MPC859PZP133
MOTOROLA
MPC866/859 Hardware Specifications
For More Information On This Product,
Go to: www.freescale.com
15
Layout Practices
These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic
discharge (ESD) protection diodes are forward-biased and excessive current can flow through these diodes.
If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 4
can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential
difference between the external bus and core power supplies on powerup and the 1N5820 diodes regulate
the maximum potential difference on powerdown.
Figure 4. Example Voltage Sequencing Circuit
9
Layout Practices
Each V
DD
pin on the MPC866/859 should be provided with a low-impedance path to the board’s supply.
Furthermore, each GND pin should be provided with a low-impedance path to ground. The power supply
pins drive distinct groups of logic on chip. The V
DD
power supply should be bypassed to ground using at
least four 0.1 μF bypass capacitors located as close as possible to the four sides of the package. Each board
designed should be characterized and additional appropriate decoupling capacitors should be used if
required. The capacitor leads and associated printed-circuit traces connecting to chip V
DD
and GND should
be kept to less than 1/2” per capacitor lead. At a minimum, a four-layer board employing two inner layers
as V
DD
and GND planes should be used.
All output pins on the MPC866/859 have fast rise and fall times. Printed-circuit (PC) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output
switching times. This recommendation particularly applies to the address and data buses. Maximum PC
trace lengths of 6” are recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the V
DD
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins. For more information,
please refer to Section 14.4.3, Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1), in the
MPC866
User’s Manual
.
10
Bus Signal Timing
The maximum bus speed supported by the MPC866/859 is 66 MHz. Higher-speed parts must be operated
in half-speed bus mode (for example, an MPC866/859 used at 100 MHz must be configured for a 50-MHz
bus). Table 7 and Table 8 show the frequency ranges for standard part frequencies.
VDDH
VDDL
1N5820
MUR420
F
Freescale Semiconductor, Inc.
n
.
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