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參數(shù)資料
| 型號： | MPC92429EIR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER LVPECL 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.5x11.5） |
| 包裝： | 帶卷 (TR) |
MPC92429 REVISION 3 DECEMBER 14, 2012
3
2012 Integrated Device Technology, Inc.
MPC92429 Data Sheet
400 MHz Low Voltage PECL Clock Synthesizer
Table 1. Pin Configurations
Pin
I/O
Default
Type
Function
XTAL_IN, XTAL_OUT
Analog
Crystal oscillator interface.
FOUT, FOUT
Output
LVPECL
Differential clock output.
TEST
Output
LVCMOS
Test and device diagnosis output.
S_LOAD
Input
0
LVCMOS
Serial configuration control input.
This inputs controls the loading of the configuration latches with the contents of the
shift register. The latches will be transparent when this signal is high, thus the data
must be stable on the high-to-low transition.
P_LOAD
Input
1
LVCMOS
Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive.
S_DATA
Input
0
LVCMOS
Serial configuration data input.
S_CLOCK
Input
0
LVCMOS
Serial configuration clock input.
M[0:8]
Input
1
LVCMOS
Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
Input
1
LVCMOS
Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD.
OE
Input
1
LVCMOS
Output enable (active high).
The output enable is synchronous to the output clock to eliminate the possibility
of runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state
(FOUT = L, FOUT = H).
GND
Supply
Ground
Negative power supply (GND).
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the
positive power supply for correct operation.
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply).
Table 2. Output Frequency Range and PLL Post-Divider N
N
Output Division
Output Frequency Range
10
0
1
200 – 400 MHz
0
1
2
100 – 200 MHz
1
0
4
50 – 100 MHz
1
8
25 – 50 MHz
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| MPC92429FA | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:400 MHz Low Voltage PECL Clock Synthesizer |
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| MPC92432AE | 功能描述:時鐘合成器/抖動清除器 FSL 1360MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92432AER2 | 功能描述:時鐘合成器/抖動清除器 FSL 1360MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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