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參數(shù)資料
| 型號： | MPC93H52ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN ZD 1:11 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:11 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
DATASHEET
3.3 V 1:11 LVCMOS Zero Delay
Clock Generator
MPC93H52
NRND
NRND – Not Recommend for New Designs
MPC93H52 REVISION 5 FEBRUARY 15, 2013
1
2013 Integrated Device Technology, Inc.
The MPC93H52 is a 3.3 V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output frequencies up
to 240 MHz and output skews lower than 200 ps the device meets the needs of
most demanding clock applications.
Features
Configurable 11 Outputs LVCMOS PLL Clock Generator
Fully Integrated PLL
Wide Range of Output Clock Frequency of 16.67 MHz to 240 MHz
Multiplication of the Input Reference Clock Frequency by 3, 2, 1, 3
2, 23,
1
3 and 12
3.3 V LVCMOS Compatible
Maximum Output Skew of 200 ps
Supports Zero-Delay Applications
Designed for High-Performance Telecom, Networking and Computing
Applications
32-Lead LQFP Package
32-Lead Pb-free Package Available
Ambient Temperature Range — 0°C to +70°C
Pin and Function Compatible to the MPC952
Not Recommend for New Designs
Functional Description
The MPC93H52 is a fully 3.3 V compatible PLL clock generator and clock driv-
er. The device has the capability to generate output clock signals of 16.67 to 240
MHz from external clock sources. The internal PLL is optimized for its frequency
range and does not require external lock filter components. One output of the MPC93H52 has to be connected to the PLL feed-
back input FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency
multiplication factor. This multiplication factor, F_RANGE, and the reference clock frequency must be selected to situate the VCO
in its specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the
FSELx pins supporting systems with different but phase-aligned clock frequencies.
The PLL of the MPC93H52 minimizes the propagation delay and, therefore, supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50
transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC93H52 is package in a 32-lead LQFP.
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
MPC93H52
LOW VOLTAGE
3.3 V LVCMOS 1:11
CLOCK GENERATOR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93H52FA | 功能描述:IC CLOCK GEN/DVR HI-DRIVE 32LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPC93H52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC93R51 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC93R51AC | 功能描述:時鐘驅(qū)動器及分配 3.3V 240MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC93R51ACR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-9 LVCMOS/LVPEC L to LVCMOS PLL Cloc RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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