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參數(shù)資料
| 型號： | MPC93H52ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN ZD 1:11 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:11 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 240MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC93H52 REVISION 5 FEBRUARY 15, 2013
5
2013 Integrated Device Technology, Inc.
MPC93H52 Data Sheet
3.3 V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR
Table 6. AC Characteristics (VCC = 3.3 V 5%, TA = 0° to 70°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input reference frequency
4 feedback
in PLL mode(2) (3)
6 feedback
8 feedback
12 feedback
Input reference frequency in PLL bypass mode(4)
2. PLL mode requires PLL_EN=0 to enable the PLL and zero-delay operation.
3. The PLL may be unstable with a divide by 2 feedback ratio.
4. In PLL bypass mode, the MPC93H52 divides the input reference clock.
50.0
33.3
25.0
16.67
50.0
120.0
80.0
60.0
40.0
250.0
MHz
fVCO
VCO lock frequency range(5)
5. The input frequency fref on CCLK must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO FB.
200
480
MHz
fMAX
Output Frequency
2 output(6)
4 output
6 output
8 output
12 output
100
50
33.3
25
16.67
240
120
80
60
40
MHz
tPWMIN
Minimum Reference Input Pulse Width
2.0
ns
tr, tf
CCLK Input Rise/Fall Time(7)
7. The MPC93H52 will operate with input rise and fall times up to 3.0 ns, but the AC characteristics, specifically t(), can only be guaranteed if
tr/tf are within the specified range.
1.0
ns
0.8 to 2.0 V
t()
Propagation Delay CCLK to FB_IN
(fref = 50 MHz)
(static phase offset)
–200
+200
ps
PLL locked
tsk(O)
Output-to-output Skew(8)
all outputs, any frequency
within QA output bank
within QB output bank
within QC output bank
8. See application section for part-to-part skew calculation.
300
200
100
ps
DC
Output duty cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ Output Disable Time
8
ns
tPZL, LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitter
output frequencies mixed
all outputs same frequency
150
25
ps
RMS
tJIT(PER) Period Jitter
output frequencies mixed
all outputs same frequency
75
20
ps
RMS
tJIT()
I/O Phase Jitter(9)
4 feedback divider RMS (1 )
6 feedback divider RMS (1 )
8 feedback divider RMS (1 )
12 feedback divider RMS (1 )
9. See application section for a jitter calculation for other confidence factors than 1
.
40
ps
BW
PLL closed loop bandwidth(10)
4 feedback
6 feedback
8 feedback
12 feedback
10. –3 dB point of PLL transfer characteristics.
2.0–8.0
1.0–4.0
0.8–2.5
0.6–1.5
MHz
tLOCK
Maximum PLL Lock Time
10
ms
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