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參數(shù)資料
| 型號(hào)： | MPC97R73FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁(yè)數(shù)： | 1/20頁(yè) |
| 文件大?。?/td> | 252K |
| 代理商： | MPC97R73FA |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC97R73/D
Rev 0, 04/2002
1
Motorola, Inc. 2002
Product Preview
3.3V/2.5V 1:12 LVCMOS PLL
Clock Generator
The MPC97R73 is a 3.3V or 2.5V compatible, 1:12 PLL based clock
generator targeted for high performance low-skew clock distribution in
mid-range to high-performance networking, computing and telecom
applications. With output frequencies up to 240 MHz and output skews
less than 300 ps1 the device meets the needs of the most demanding
clock applications.
Features
1:12 PLL based low-voltage clock generator
2.5V or 3.3V power supply
Internal power–on reset
Generates clock signals up to 240 MHz
Maximum output skew of 300 ps1
Differential PECL reference clock input
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Synchronous output clock stop circuitry for each individual output for
power down support
Drives up to 24 clock lines
Ambient temperature range 0°C to +85°C
Pin and function compatible to the MPC973
Functional Description
The MPC97R73 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC97R73 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.
The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to
match the VCO frequency range. The MPC97R73 features an extensive level of frequency programmability between the 12
outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In
addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a
non–binary factor. The MPC97R73 also supports the 180 phase shift of one of its output banks with respect to the other output
banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation
of system baseline timing signals.
The REF_SEL pin selects the *1 or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS
compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for
test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the
PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
MPC97R73. The MPC97R73 has an internal power–on reset.
The MPC97R73 is fully 2.5V and 3.3V compatible and requires no external loop filter components. All inputs (except PCLK)
accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
W
transmission lines. For series terminated transmission lines, each of the MPC97R73 outputs can drive one or two traces giving
the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead
LQFP package.
1. Final specification of this parameter is pending characterization.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D
MPC97R73
3.3V/2.5V 1:12 LVCMOS
PLL CLOCK GENERATOR
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| MPC9817EN | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9817ENR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9817SD | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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